We have proposed and demonstrated “PN-Body Tied SOI FET (PNBT)” which shows the super steep subthreshold slope (SS<1mV/dec) over 3 to 5 decades of the drain current with the ultralow drain voltage of 0.1V, at IEDM2015, IEEE S3S 2016, also accepted on IEEE J. EDS 2018. At IEEE EDTM2018, we have also demonstrated the P-channel PNBT, which will open possibility of realizing the super steep SS CMOS device for ultralow power IoT edge applications. The PNBT will be a near future candidate of steep slope devices, instead of tunnel FETs and negative capacitance FETs. In this talk, I introduce the current status on our PNBT research and also talk about PNBT applying to RF Energy harvesting, where the high efficiency rectification on the ultralow input power below -30dBm is a key technical challenge.

Jiro　Ida　 Received the B.S. M.S. and PhD degrees in Applied Physics from University of Tokyo in 1981, 1983 and 1998, respectively. During 1985-2009, he had been in OKI Electric Industry Co. Ltd., where he had leaded the R&D of CMOS Logic devices & integrations, and FD-SOI technology. He moved to Kanazawa Institute of Technology in 2009. Since then, he has been a professor of the department of Electrical and Electronic Engineering. His current research area covers Ultra low power devices, RF Energy Harvesting and Interface evaluation. He had been served as a Japan PIDS (Process Integration and Device Structure) leader and a Japan PIDS member of ITRS (the International Technology Roadmap for Semiconductors), a program committee member and a conference secretary of VLSI Technology symposium, a program committee member of IEEE SOI conference, a SOI subcommittee member of CMC (Compact Model Council) and an education committee and a technical program committee member of IEEE EDTM.